The MPEG-2 and MPEG-4 standards are well-known in the art for coding and storing multimedia video and associated audio information. When MPEG multimedia data is transmitted over a network from a source device to a destination device, it is important that the transmitted data be synchronized at the destination device by matching the destination device's clock to the source device's clock. It is known in the art to use a phase locked loop (PLL) at the destination device to synchronize the source device's clock with the destination device's clock.
Generally, as is known in the art, MPEG-2 and MPEG-4 standards call for multimedia data to be coded and stored in discrete data packets. The format of each data packet provides for a “clock-stamp” reference value in which a time reference value from the source device's clock can be stored prior to transmission across the network. When a stream of data packets are transmitted over a network, only a selected sample of the data packets actually include a clock-stamp time reference stored in the reserved data bytes. The destination device compares the clock-stamp time references that it receives in the to transmitted MPEG data with the instant time provided by the destination device's local clock. From this comparison, a phase error can be derived. A PLL uses the phase error to adjust the decoder clock. Methods of comparing clock-stamp time references with the destination device's clock to determine a phase error and enable a PLL to adjust the destination device's clock to match the source device's clock are known in the art.
For purposes of synchronizing the device's respective clocks, MPEG semantics assume a constant delay network between the source device and the destination device. However, it is difficult, if not impossible, to maintain a constant network delay. Non-constant network delays, known as “jitter”, can result in a degradation of the video playback. Jitter results in data packets arriving at the destination device in a non-uniform manner, which impedes effective clock synchronization by the PLL. Specifically, the PLL must perform additional filtering in order to correctly estimate the STC clock values. This, in turn, slows down the responsiveness of the PLL and affects the maximum phase error introduced by the PLL between the clock-stamped reference values encoded from the source device's clock and the corresponding destination device's time clock references. To assure a stable recovery of the source device's clock values (also referred to as the system clock (STC)) by the PLL, de-jittering algorithms must be performed before the encoded clock values are passed to the PLL.